1. Field of the Invention
The present invention relates to a semiconductor structure. More particularly, the present invention relates to formation of an etch stop and diffusion layer composite in a semiconductor structure. In particular, the present invention relates to a damascene process that uses an etch stop and a diffusion barrier layer composite.
2. Description of Related Art
Multiple levels of interconnect are being developed for integrated circuits. In such an integrated circuit, patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by an insulating layer of material such as, for example, silicon dioxide. The insulating layer is often referred to as an interlayer dielectric (ILD). The conductive materials are typically a metal or metal alloy. Connections between the conductive material at the various interconnect levels are made by forming openings in the insulating layers and providing an electrically conductive structure such that the patterned conductive material from different interconnect levels are brought into electrical contact with each other. These electrically conductive structures are often referred to as contacts or vias.
Semiconductor device features continue to shrink to accommodate more transistors per silicon wafer and improve device performance. Shrinking dimensions, however, results in an increased capacitance between metal lines. An increase in capacitance seriously degrades device performance because signal delay is proportional to the product of resistance with capacitance. One technique for increasing speed while reducing power consumption is to replace the traditional aluminum and aluminum alloy interconnects found on integrated circuits with a metal such as copper, which offers lower electrical resistance. Those skilled in the electrical arts will appreciate that by reducing resistance, electrical signals may propagate more quickly through the interconnect pathways on an integrated circuit. Furthermore, because the resistance of copper is significantly less than that of aluminum, the cross-sectional area of a copper interconnect line, as compared to an aluminum interconnect line, may be made smaller without incurring increased signal propagation delays based on the resistance of the interconnect.
As noted above, copper has electrical advantages, such as lower resistance per cross-sectional area, and greater immunity to electromigration. For all these reasons, manufacturers of integrated circuits find it desirable to include copper in their products. Another approach for reducing the resistance-capacitance (RC) delay and thence improving device performance is to use low-dielectric-constant (low-k) materials as an ILD in semiconductor devices because capacitance is proportional to the dielectric constant of the ILD.
The process integration of copper and ILD can be difficult due to the risk of etch-through of an underlying ILD layer at unlanded vias, and undesired reaction on underlying copper during via etch. In addition, copper can readily diffuse into ILD that adversely affect the quality of device such as leakage current and reliability between the lines. As a result, a separate layer is usually added to the integration flow to act as an etch stop and a diffusion barrier.
The diffusion barrier property of the added layer, however, results in a material with a high dielectric constant. For example, silicon nitrides (SixNyHz, in both stoichometric and solid solution ratios) have a dielectric constant of about 6.5 to about 10, and silicon carbides (SiwCxNyHz in both stoichometric and solid solution ratios) have a dielectric constant of about 4.0 to about 5.0. This negatively impacts the overall effective dielectric constant (keff) between the metal lines. Consequently, increased RC delay results. RC delay can be minimized by reducing the thickness of the added layer, but this is prevented by the etch selectivity requirements for the added layer as an etch stop.